Build the FIFO. From scratch.

Build a parameterized synchronous FIFO from scratch in SystemVerilog.

Interface

module sync_fifo #(
    parameter DEPTH = 16,   // power of 2
    parameter WIDTH = 8
) (
    input  logic             clk,
    input  logic             rst,     // synchronous, active-high
    input  logic             wr_en,
    input  logic             rd_en,
    input  logic [WIDTH-1:0] din,
    output logic [WIDTH-1:0] dout,
    output logic             full,
    output logic             empty,
    output logic [$clog2(DEPTH):0] count   // number of valid entries, 0..DEPTH
);

Requirements

Standard circular-buffer FIFO, one write port, one read port.
wr_en && !full writes din on that clock edge.
rd_en && !empty presents the oldest entry on dout (registered).
full/empty/count must be correct including the edge cases: simultaneous read+write, back-to-back writes to exactly fill it, back-to-back reads to exactly drain it, and pointer wraparound.
No inferred latches, no combinational loops.

The challenge

Implement the interface in design.sv. Verify reset, simultaneous reads and writes, full and empty boundaries, and pointer wraparound. Aim to write it in under 20 minutes.

Download the original problem. Its references to Q1 and tb.sv refer to materials not included here.